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DATA SHEET
PD753012, 753016, 753017
4-BIT SINGLE-CHIP MICROCONTROLLER
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD753017 is one of the 75XL series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. It has an on-chip LCD controller/driver with a larger ROM capacity and extended CPU functions compared with the conventional PD75316B, and can provide high-speed operation. It can be supplied in a small plastic TQFP package (12 x 12 mm) and is suitable for small sets using LCD panels. For details of functions refer to the following User's Manual.
PD753017 User's Manual : U11282E
FEATURES
* Low voltage operation: VDD = 2.2 to 5.5 V * Can be driven by two 1.5 V batteries * On-chip memory * Program memory (ROM): 12288 x 8 bits (PD753012) 16384 x 8 bits (PD753016) 24576 x 8 bits (PD753017) * Data memory (RAM): 1024 x 4 bits * Capable of high-speed operation and variable instruction execution time for power saving * 0.95, 1.91, 3.81, 15.3 s (at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (at 6.0 MHz operation) * 122 s (at 32.768 kHz operation) * Internal programmable LCD controller/driver * Small plastic TQFP (12 x 12 mm) * Suitable for small sets such as cameras * One-time PROM: PD75P3018
APPLICATION
Remote controllers, camera-contained VCRs, cameras, gas meters, etc.
ORDERING INFORMATION
Part number Package 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
PD753012GC-XXX-3B9 PD753012GK-XXX-BE9 PD753016GC-XXX-3B9 PD753016GK-XXX-BE9 PD753017GC-XXX-3B9 PD753017GK-XXX-BE9
Remark
XXX indicates a ROM code suffix.
In this document, unless otherwise specified, the description is made based on PD753017 as typical product.
The information in this document is subject to change without notice. Document No. U10140EJ2V0DS00 (2nd edition) Date Published December 1997 N Printed in Japan
The mark
shows major revised points.
(c)
1995
PD753012, 753016, 753017
FUNCTIONAL OUTLINE
Parameter Instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (main system clock: at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (main system clock: at 6.0 MHz operation) * 122 s (subsystem clock: at 32.768 kHz operation) ROM 12288 x 8 bits (PD753012) 16384 x 8 bits (PD753016) 24576 x 8 bits (PD753017) RAM General-purpose register 1024 x 4 bits * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 8 16 8 8 Also used for segment pins Withstands 13 V, on-chip pull-up resistors can be specified by using mask option On-chip pull-up resistors can be specified by using software: 23
On-chip memory
Input/ output port
CMOS input CMOS input/output CMOS output N-ch open-drain input/output Total
40 * Segment number selection * Display mode selection : 24/28/32 segments (can be changed to CMOS output port in 4 time-unit; max. 8) : Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias)
LCD controller/driver
On-chip split resistor for LCD drive can be specified by using mask option Timer 5 channels * 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter, carrier generator, or timer with gate) * Basic interval timer/watchdog timer: 1 channel * Watch timer: 1 channel * 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit * 2-wire serial I/O mode * SBI mode 16 bits * , 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) (main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) External: 3, Internal: 5 External: 1, Internal: 1 * Ceramic or crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation STOP/HALT mode VDD = 2.2 to 5.5 V * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) * 2, 4, 32 kHz
Serial interface
Bit sequential buffer Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupts Test input System clock oscillator
Standby function Power supply voltage Package
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PD753012, 753016, 753017
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 5 2. BLOCK DIAGRAM ............................................................................................................................... 7 3. PIN 3.1 3.2 3.3 3.4 FUNCTION .................................................................................................................................... 8 Port Pins ...................................................................................................................................... 8 Pins Other than Port Pins ........................................................................................................ 10 Pin Input/Output Circuits ......................................................................................................... 12 Recommended Connection for Unused Pins ......................................................................... 14
4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE ...................................... 15 4.1 Differences between Mk I Mode and Mk II Mode .................................................................... 15 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 16 5. MEMORY CONFIGURATION ............................................................................................................17 6. PERIPHERAL HARDWARE FUNCTIONS ....................................................................................... 21 6.1 Digital Input/Output Ports ........................................................................................................ 21 6.2 Clock Generator ........................................................................................................................22 6.3 Subsystem Clock Oscillator Control Functions .................................................................... 23 6.4 Clock Output Circuit .................................................................................................................24 6.5 Basic Interval Timer/Watchdog Timer ..................................................................................... 25 6.6 Watch Timer ..............................................................................................................................26 6.7 Timer/Event Counter .................................................................................................................27 6.8 Serial Interface ..........................................................................................................................31 6.9 LCD Controller/Driver ............................................................................................................... 33 6.10 Bit Sequential Buffer ... 16 Bits ...............................................................................................35 7. INTERRUPT FUNCTION AND TEST FUNCTION ........................................................................... 36 8. STANDBY FUNCTION .......................................................................................................................38 9. RESET FUNCTION ............................................................................................................................ 39 10. MASK OPTION .................................................................................................................................. 42 11. INSTRUCTION SETS AND THEIR OPERATIONS ........................................................................ 43 12. ELECTRICAL SPECIFICATIONS ...................................................................................................... 55 13. PACKAGE DRAWINGS ..................................................................................................................... 68 14. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 70
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PD753012, 753016, 753017
APPENDIX A PD75316B, 753017 AND 75P3018 FUNCTION LIST ................................................ 72 APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 74 APPENDIX C RELATED DOCUMENTS ................................................................................................. 78
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PD753012, 753016, 753017
1. PIN CONFIGURATION (TOP VIEW)
* 80-pin plastic QFP (14 x 14 mm)
PD753012GC-XXX-3B9, 753016GC-XXX-3B9, PD753017GC-XXX-3B9
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
PD753012GK-XXX-BE9, 753016GK-XXX-BE9, PD753017GK-XXX-BE9
S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1
S11 S10 S9 S8
P60/KR0 X2 X1 Note IC XT2 XT1 VDD P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P12/INT2/TI1/TI2 P11/INT1 P10/INT0 P03/SI/SB1
Note Connect the IC (Internally Connected) pin directly to VDD.
P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0
COM0 COM1 COM2
COM3 BIAS VLC0
VLC1
VLC2 P40 P41 P42 P43 VSS
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PD753012, 753016, 753017
Pin Name P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 BP0-BP7 KR0-KR7 SCK SI SO SB0, SB1 RESET S0-S31 : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Bit Port : Key Return : Serial Clock : Serial Input : Serial Output : Serial Bus 0, 1 : Reset Input : Segment Output 0-31 VLC0-VLC2 BIAS LCDCL SYNC TI0-TI2 PTO0-PTO2 BUZ PCL INT2 X1, X2 XT1, XT2 VDD VSS IC : LCD Power Supply 0-2 : LCD Power Supply Bias Control : LCD Clock : LCD Synchronization : Timer Input 0-2 : Programmable Timer Output 0-2 : Buzzer Clock : Programmable Clock : External Test Input 2 : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 : Positive Power Supply : Ground : Internally Connected
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4
COM0-COM3 : Common Output 0-3
6
2. BLOCK DIAGRAM
PTO1/P21
TI1/TI2/ P12/INT2
PTO2/P22/PCL TOUT0 INTT2
INTT1
TIMER/EVENT COUNTER #1
TIMER/EVENT COUNTER #2
BASIC INTERVAL /WATCHDOG TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 TOUT0
PROGRAM Note 1 COUNTER
PORT0 PORT1 SP (8) ALU CY SBS BANK PORT2
4 4 4 4 4 4 4 4
P00-P03 P10-P13 P20-P23
PORT3 PORT4
P30-P33 P40-P43 P50-P53 P60-P63 P70-P73
BUZ/P23
WATCH TIMER GENERAL REG. INTW fLCD ROMNote 2 PROGRAM MEMORY DECODE AND CONTROL PORT5 PORT6 PORT7
SI/SB1/P03 SO/SB0/P02 SCK/P01
CLOCKED SERIAL INTERFACE INTCSI TOUT0
RAM DATA MEMORY 1024 X 4 BITS
24 8
S0-S23 S24/BP0S31/BP7 COM0-COM3 VLC0-VLC2 BIAS LCDCL/P30 SYNC/P31
PD753012, 753016, 753017
INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60- 8 KR7/P73 BIT SEQ. BUFFER (16) fx/2N CLOCK OUTPUT CONTROL CLOCK DIVIDER INTERRUPT CONTROL CPU CLOCK
SYSTEM CLOCK GENERATOR
LCD CONTROLLER /DRIVER
4 3
fLCD STAND BY CONTROL
SUB
MAIN
PCL/PTC2/P22
XT1 XT2 X1 X2
IC
VDD
VSS RESET
Notes 1. 2.
PD753012 and 753016 have a 14-bit configuration, and PD753017 has a 15-bit configuration.
Capacity of the ROM depends on the product.
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PD753012, 753016, 753017
3. PIN FUNCTION 3.1 Port Pins (1/2)
Dual Function Pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1 TI1/TI2/INT2 TI0 Input/Output PTO0 PTO1 PCL/PTO2 BUZ Input/Output LCDCL SYNC - - Input/Output - Programmable 4-bit input/output port (PORT3). This port can be specified input/output in bit units. On-chip pull-up resistor can be specified in software in 4-bit units. N-ch open-drain 4-bit input/output port (PORT4). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. x Input E-B 4-bit input port (PORT1). On-chip pull-up resistors can be specified in software in 4-bit units. Noise eliminator can be selected (Only P10/INT0) 4-bit input/output port (PORT2). On-chip pull-up resistors can be specified in software in 4-bit units. x input 8-bit I/O x I/O Circuit TYPE Note 1 B F -A F -B M -C B -C
Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P40-P43 Note 2
Input/Output Input Input/Output Input/Output Input/Output Input
Function 4-bit input port (PORT0). For P01 to P03, on-chip pull-up resistors can be specified in software in 3-bit units.
At Reset Input
x
Input
E-B
High level (when pull-up resistors are contained) or high impedance
M-D
P50-P53 Note 2
Input/Output
-
High level (when pull-up resistors are provided) or high impedance
M-D
Notes 1. 2.
Circled characters indicate the Schmitt-trigger input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed.
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PD753012, 753016, 753017
3.1 Port Pins (2/2)
Dual Function Pin KR0 KR1 KR2 KR3 Input/Output KR4 KR5 KR6 KR7 Output S24 S25 S26 S27 Output S28 S29 S30 S31 1-bit output port (BIT PORT) Also used for segment output pins. x Note 2 H-A 8-bit I/O I/O Circuit TYPE Note 1 F -A
Pin Name P60 P61 P62 P63 P70 P71 P72 P73 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7
Input/Output Input/Output
Function Programmable 4-bit input/output port (PORT6). This port can be specified for input/output bit-wise. On-chip pull-up resistors can be specified in software in 4-bit units. 4-bit input/output port (PORT7). On-chip pull-up resistors can be specified in software in 4-bit units.
At Reset Input
Input
F -A
Notes 1. 2.
Circled characters indicate the Schmitt-trigger input. For BP0 to BP7, VLC1 is selected as an input source. The output levels differ depending on BP0 to BP7 and the external circuit of the VLC1.
Example BP0 to BP7 are connected each other internally in the PD753017 as shown below. Therefore, the output levels of BP0 to BP7 are determined by the levels of R1, R2, and R3
PD753017
VDD
R2 BP0 VLC1 ON
R1 ON
BP1
R3
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PD753012, 753016, 753017
3.2 Pins Other than Port Pins (1/2)
Dual Function Pin P13 P12/INT2 I/O Circuit TYPE Note 1 B -C
Pin Name TI0 TI1 TI2 PTO0 PTO1 PTO2 PCL BUZ
Input/Output Input
Function Inputs external event pulses to the timer/event counter.
At Reset Input
Output
P20 P21 P22/PCL P22/PTO2 P23
Timer/event counter output
Input
E-B
Clock output Any frequency output (for buzzer output or system clock trimming) Serial clock input/output Serial data output Serial bus data input/output Serial data input Serial bus data input/output Edge detection vectored interrupt input (both rising edge and falling edge detection)
Edge detection vectored interrupt input (detection edge can be selected) Noise eliminator can be selected. (Only P10/INT0) Edge-detection-testable input With noise eliminator asynchronous selection possible Asynchronous Asynchronous
SCK SO/SB0
Input/Output
P01 P02
Input
F -A F -B
SI/SB1
P03
M -C
INT4
Input
P00
Input
B
INT0
Input
P10
Input
B -C
INT1 INT2 KR0-KR3 KR4-KR7 S0-S23 S24-S31 COM0-COM3 VLC0-VLC2 Input Input Input Output Output Output -
P11 P12/TI1/TI2 P60-P63 P70-P73 - BP0-BP7 - -
Input Input Input Note 2 Note 2 Note 2 -
B -C F -A F -A G-D H-A G-B -
Falling edge detection testable input Falling edge detection testable input Segment signal output Segment signal output Common signal output LCD drive power On-chip split resistor is enable (mask option). Output for external split resistor disconnect Clock output for externally expanded driver Clock output for externally expanded driver sync Crystal/ceramic connection pin for the main system clock oscillator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2.
BIAS LCDCL SYNC X1 X2
Note 4
Output Output Output Input -
- P30 P31 -
Note 3 Input Input -
- E-B E-B -
Note 4
Notes 1. 2. 3. 4.
Circled characters indicate the Schmitt trigger input. Each displays output selects the following VLCX as input source. S0-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0. When a split resistor is contained ....... When no split resistor is contained ...... P30 and P31. Low level High impedance
These pins are provided for future system expansion. At present, these pins are used only as pins
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PD753012, 753016, 753017
3.2 Pins Other than Port Pins (2/2)
Dual Function Pin - I/O Circuit TYPE Note -
Pin Name XT1 XT2
Input/Output Input -
Function Crystal connection pin for the subsystem clock oscillator. When the external clock is used, input the external clock to pin XT1. In this case, pin XT2 must be left unconnected. Pin XT1 can be used as a 1bit input (test) pin. System reset input (low level active) Internally connected. Connect directly to VDD. Positive power supply GND
At Reset -
RESET IC VDD VSS
Input - - -
- - - -
- - - -
B - - -
Note
Circled characters indicate the Schmitt trigger input.
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PD753012, 753016, 753017
3.3 Pin Input/Output Circuits
The PD753017 pin input/output circuits are shown schematically.
TYPE A TYPE D VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT
CMOS specification input buffer. TYPE B
Push-pull output that can be placed in output high impedance (both P-ch, N-ch off). TYPE E-B
VDD P.U.R. P.U.R. enable data Type D output disable P-ch
IN
IN/OUT
Schmitt trigger input having hysteresis characteristic.
Type A
P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A
VDD VDD P.U.R. P.U.R. enable P.U.R. enable data output disable IN Type B Type D P.U.R. P-ch
P-ch
IN/OUT
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
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PD753012, 753016, 753017
TYPE F-B TYPE H-A P.U.R. P.U.R. enable output disable (P) data output disable output disable (N) N-ch VDD P-ch IN/OUT bit port data output disable Type D P-ch SEG data Type G-D IN/OUT
VDD
P.U.R. : Pull-Up Resistor TYPE G-B TYPE M-C VDD VLC0 P.U.R. VLC1 P-ch N-ch P.U.R. enable P-ch IN/OUT OUT COM data N-ch VLC2 N-ch P.U.R. : Pull-Up Resistor TYPE G-D TYPE M-D VDD VLC0 data P-ch N-ch output disable Input instruction OUT SEG data N-ch VLC2 N-ch VDD P-ch P.U.R.
Note
data output disable
N-ch
P-ch
P.U.R. (Mask Option) IN/OUT N-ch (+13 V withstand voltage)
VLC1
Voltage limitation circuit (+13 V withstand voltage)
P.U.R. : Pull-Up Resistor Note This pull-up resistor operates only when an input instruction is executed if the pull-up resistor is not connected by the mask option. (When the pin is at low level, current flows from VDD to the pin.)
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PD753012, 753016, 753017
3.4 Recommended Connection for Unused Pins
Table 3-1. List of Recommended Connection for Unused Pins
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0, P11/INT1 P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PTO2/PCL P23/BUZ P30/LCDCL P31/SYNC P32 P33 P40-P43 P50-P53 Input state : Connect to VSS. Output state : Connected to VSS. (Do not connect the pull-up resistor by mask option). P60/KR0-P63/KR3 P70/KR4-P73/KR7 S0-S23 S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 BIAS Connect to VSS. Only if all of VLC0-VLC2 are unused, connect to VSS. In other cases, leave unconnected. Connect to VSS. Leave unconnected. Directly connect to VDD. Input state : Individually connected to VSS or VDD via resistor. Output state : Leave unconnected. Leave unconnected. Input state : Individually connect to VSS or VDD via resistor. Output state : Leave unconnected. Connected to VSS. Connect to VSS or VDD. Recommended Connection Connect to VSS or VDD. Independently connect to VSS or VDD via resistor.
XT1 XT2 IC
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PD753012, 753016, 753017
4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE 4.1 Differences between Mk I Mode and Mk II Mode
The CPU of PD753017 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the stack bank select register (SBS). * Mk I mode: * Mk II mode: Upward compatible with PD75316B. Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes. Incompatible with PD75316B. Can be used in all the 75XL CPU's including those products whose ROM capacity is more than 16K bytes. Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I Mode Program memory (bytes) * PD753012 : 12288 * PD753016, 753017 : 16384 Mk II Mode * PD753012 : 12288 * PD753016 : 16384 * PD753017 : 24576 3 bytes
Number of stack bytes for subroutine instructions BRA !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction
2 bytes
Not available
Available
3-machine cycles 2-machine cycles
4-machine cycles 3-machine cycles
Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This mode enhances the software compatibility with products which have more than 16K bytes. When Mk II mode is selected, the number of stack bytes (usable area) in the execution of a subroutine call instruction increases by 1 per stack compared to Mk I mode. Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle. Therefore, when more importance is attached to RAM utilization or throughput than software compatibility, use the Mk I mode.
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PD753012, 753016, 753017
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 10XXB Note at the beginning of a program. When using the Mk II mode, it must be initialized to 00XXBNote. Figure 4-1. Stack Bank Select Register Format
Address F84H
3 SBS3
2
1
0 SBS0
Symbol SBS
SBS2 SBS1
Stack area specification 0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3
0
0 must be set in the bit 2 position.
Mode switching specification 0 1 Mk II mode Mk I mode
Note
The desired numbers must be set in the XX positions.
Caution Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode.
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PD753012, 753016, 753017
5. MEMORY CONFIGURATION
* Program memory (ROM) ............... 12288 x 8 bits (PD753012) ............... 16384 x 8 bits (PD753016) ............... 24576 x 8 bits (PD753017) * Data memory (RAM) * * Data area ...1024 words x 4 bits (000H to 3FFH) Peripheral hardware area...128 x 4 bits (F80H to FFFH) Figure 5-1. Program Memory Map (1/3) (a) PD753012
7 0000H MBE 6 RBE 5 0
Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address INTBT/INT4 start address
(high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) CALL !addr instruction subroutine entry address CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr1, BRA !addr1Note or CALLA !addr1Note instruction
0004H
MBE
RBE
INT0 start address INT0 start address
0006H
MBE
RBE
INT1 start address INT1 start address
0008H
MBE
RBE
INTCSI start address INTCSI start address
BRCB !caddr instruction branch address
000AH
MBE
RBE
INTT0 start address INTT0 start address
000CH
MBE
RBE
INTT1, INTT2 start address (high-order 6 bits) INTT1, INTT2 start address (Iow-order 8 bits) BR $addr instruction relative branch address (-15 to -1, +2 to +16)
0020H GETI instruction reference table 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH Branch destination address and subroutine entry address when GETI instruction is executed
BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE, BR PCXA instruction.
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PD753012, 753016, 753017
Figure 5-1. Program Memory Map (2/3) (b) PD753016
7 0000H MBE 6 RBE 5 0
Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address INTBT/INT4 start address
(high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) CALL !addr instruction subroutine entry address CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction
0004H
MBE
RBE
INT0 start address INT0 start address
0006H
MBE
RBE
INT1 start address INT1 start address
0008H
MBE
RBE
INTCSI start address INTCSI start address
BRCB !caddr instruction branch address
000AH
MBE
RBE
INTT0 start address INTT0 start address
000CH
MBE
RBE
INTT1,INTT2 start address (high-order 6 bits) INTT1,INTT2 start address (Iow-order 8 bits) BR $addr instruction relative branch address (-15 to -1, +2 to +16) GETI instruction reference table
0020H 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH
Branch destination address and subroutine entry address when GETI instruction is executed
BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE, BR PCXA instruction.
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PD753012, 753016, 753017
Figure 5-1. Program Memory Map (3/3) (c) PD753017
7 0000H MBE 6 RBE 5 0
Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address INTBT/INT4 start address
(high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) CALL !addr instruction branch address BR BCDE BR BCXA branch address BR !addr instruction branch address CALLF !faddr instruction entry address
0004H
MBE
RBE
INT0 start address INT0 start address
0006H
MBE
RBE
INT1 start address INT1 start address
BRCB !caddr instruction branch address
0008H
MBE
RBE
INTCSI start address INTCSI start address
000AH
MBE
RBE
INTT0 start address INTT0 start address
000CH
MBE
RBE
INTT1,INTT2 start address (high-order 6 bits) INTT1,INTT2 start address (Iow-order 8 bits)
0020H GETI instruction reference table 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH 4000H 4FFFH 5000H 5FFFH
GETI instruction branch/call address
BRA !addr1Note instruction branch address
CALLA !addr1Note instruction branch address
BR $addr instruction relative branch address (-15 to -1, +2 to +16) BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Note Can be used in Mk II mode only. Caution The interrupt vector start address shown above consists of 14 bits. Set it in 16K space (0000H3FFFH). Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE, BR PCXA instruction.
19
PD753012, 753016, 753017
Figure 5-2. Data Memory Map
Data memory 000H General-purpose register area 01FH 020H 0 256 x 4 (224 x 4) 0FFH 100H 256 x 4 (224 x 4) 1DFH 1E0H Display data memory Stack areaNote Data area static RAM (1024 x 4) 256 x 4 2 1FFH 200H (32 x 4) 1 (32 x 4) Memory bank
2FFH 300H
256 x 4
3
3FFH
Not incorporated
F80H
Peripheral hardware area
128 x 4
15
FFFH
Note For stack area, one memory bank can be selected among memory bank 0-3.
20
PD753012, 753016, 753017
6. PERIPHERAL HARDWARE FUNCTIONS 6.1 Digital Input/Output Ports
There are four types of I/O ports as follows. * CMOS input (PORT0, 1) * CMOS input/output (PORT2, 3, 6, 7) * N-channel open-drain input/output (PORT4, 5) * Bit port output (BP0-BP7) Total : : : 8 8 8 40 Table 6-1. Types and Features of Digital Ports
Port (Pin Name) PORT0 (P00-P03) PORT1 (P10-P13) PORT2 (P20-P23) PORT3 (P30-P33) PORT4 (P40-P43) PORT5 (P50-P53) PORT6 (P60-P63) 4-bit I/O (N-channel open-drain, 13 V withstanding) 4-bit I/O 4-bit I/O Function 4-bit input Operation & Features Dual function pins also function as output pins depending on the operation mode when the serial interface function is used. Dedicated 4-bit I/O port Remarks Also used for the INT4, SCK, SO/SB0, SI/SB1 pins. Also used for the INT0INT2 and TI0-TI2 pins. Also used for the PTO0PTO2, PCL, BUZ pins. Also used for the LCDCL, SYNC pins. On-chip pull-up resistor can be specified bit-wise by mask option.
: 16
Can be set to input mode or output mode in 4-bit units. Can be set to input mode or output mode in 1/4 bit units. Can be set to input mode or output mode in 4-bit units. Ports 4 and 5 are paired and data can be input/ output in 8-bit units.
Can be set to input mode or output mode in 1/4-bit units. Can be set to input mode or output mode in 4-bit units.
Ports 6 and 7 are paired and data can be input/ output in 8-bit units.
Also used for the KR0-KR3 pins.
PORT7 (P70-P73)
Also used for the KR4-KR7 pins.
BP0-BP7
1-bit output
Outputs data bit-wise. Can be switched to LCD drive segment output S24-S31 by software.
--
21
PD753012, 753016, 753017
6.2 Clock Generator
Operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC). The two clocks, the main system clock and subsystem clock, are available. The instruction excution time can be altered. * 0.95 s, 1.91 s, 3.81 s, 15.3 s (main system clock : at 4.19 MHz operation) * 0.67 s, 1.33 s, 2.67 s, 10.7 s (main system clock : at 6.0 MHz operation) * 122 s (subsystem clock : at 32.768 kHz operation) Figure 6-1. Clock Generator Block Diagram
* Basic interval timer (BT) * Timer/event counter * Serial interface * Watch timer * LCD controller/driver * INT0 noise eliminator * Clock output circuit 1/1~1/4096 Divider 1/2 1/4 1/16
XT1 VDD XT2 X1 VDD X2 Main system clock oscillator fX Subsystem clock oscillator fXT LCD controller/driver Watch timer
Selector WM.3 SCC SCC3 Oscillation stop Selector
Divider 1/4 * CPU * INT0 noise eliminator * Clock output circuit
Internal bus
SCC0 PCC PCC0 PCC1 4 PCC2 HALTNote STOPNote PCC3 R Q HALT F/F S
PCC2, PCC3 Clear
STOP F/F Q S
Wait release signal from BT RESET signal
R
Standby release signal from interrupt control circuit
Note Instruction execution Remarks 1. 2. 3. 4. 5. 6. fX = Main system clock frequency fXT = Subsystem clock frequency = CPU clock PCC: Processor Clock Control Register SCC: System Clock Control Register One clock cycle (tCY) of equal to one machine cycle of the instruction.
22
PD753012, 753016, 753017
6.3 Subsystem Clock Oscillator Control Functions
The PD753017 subsystem clock oscillator has the following two control functions. * Selects by software whether an on-chip feedback resistor is to be used or notNote. * Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply current is high (VDD 2.7 V). Note When not using the subsystem clock, set SOS.0 to 1 in software (on-chip feedback resistor is not used), connect XT1 to VSS, and leave XT2 unconnected, so that the current consumption of the subsystem clock oscillator can be reduced. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (Refer to Figure 6-2.)
Figure 6-2. Subsystem Clock Oscillator
VDD SOS.0
Feedback resistor Inverter SOS.1 XT1 XT2
PD753017
VDD
23
PD753012, 753016, 753017
6.4 Clock Output Circuit
The clock output circuit is provided to output the clock pulses from the P22, PTO2, and PCL pins to the remote control waveform outputs and peripheral LSI's, etc. * Clock output (PCL) : , 524, 262, 65.5 kHz (at 4.19 MHz operation) , 750, 375, 93.8 kHz (at 6.0 MHz operation) Figure 6-3. Clock Output Circuit Block Diagram
From clock generator fX/23 Selector fX/24 fX/26 From timer/event counter (channel 2)
Selector
Output buffer PCL/PTO2/P22
PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch
Bit 2 of PMGB Port 2 I/O mode specification bit
4 Internal bus
Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable.
24
PD753012, 753016, 753017
6.5 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions. * Interval timer operation to generate a reference time interrupt * Watchdog timer operation to detect a runaway of program and reset the CPU * Selects and counts the wait time when the standby mode is released * Reads the contents of counting Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram
From clock generator fX/25 fX/27 MPX fX/29 fX/212 3 BT Clear Clear
Basic interval timer (8-bit frequency divider)
Set
BT interrupt request flag Vectored interrupt IRQBT request signal
Wait release signal when standby is released.
Internal reset signal WDTM SET1Note 1
BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 8 Internal bus
Note Instruction execution
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PD753012, 753016, 753017
6.6 Watch Timer
The PD753017 has one channel of watch timer. The watch timer has the following functions. * Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW. * 0.5 sec interval can be created by both the main system clock and subsystem clock. Take fX = 4.194304 MHz for the main system clock frequency and fXT = 32.768 kHz for the subsystem clock. * Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. * Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23 and BUZ pins, usable for buzzer and trimming of system clock frequencies. * Clears the frequency divider to make the clock start with zero seconds. Figure 6-5. Watch Timer Block Diagram
fW (512 Hz : 1.95 ms) 26 fW (256 Hz : 3.91 ms) 27 fX 128 From clock generator (32.768 kHz) fXT (32.768 kHz) Selector
fLCD
fW (32.768 kHz) 4 kHz 2 kHz fW fW 23 24
Divider
fW 214 2 Hz 0.5 sec
Selector INTW IRQW set signal
Clear
Selector
Output buffer P23/BUZ
WM WM7 0 WM5 WM4 WM3 WM2 WM1 WM0
PORT2.3 P23 output latch
PMGB bit 2 Port 2 input/ output mode
8
Bit test instruction
Internal bus
The values enclosed in parentheses are applied when fX = 4.194304 MHz and fXT = 32.768 kHz.
26
PD753012, 753016, 753017
6.7 Timer/Event Counter
The PD753017 has three channels of timer/event counter. The timer/event counter has the following functions. * Programmable interval timer operation * Square wave output of any frequency to the PTOn pin * Event counter operation * Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency divider operation). * Supplies the serial shift clock to the serial interface circuit. * Calls the counting status. The timer/event counter operates in the following four modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter
Channel Channel 0 Mode 8-bit timer/event counter mode Gate control function PWM pulse generator mode 16-bit timer/event counter mode Gate control function Carrier generator mode x x x x x
Note Note
Channel 1
Channel 2
x x
Note Used for gate control signal generation
27
28
8 - PORT1.3 Input buffer TI0/P13 fx/24 From fx/26 clock fx/28 generator fx/210 MPX
Figure 6-6. Timer/Event Counter Block Diagram (channel 0)
Internal bus SET1Note TM0 TM06 TM05 TM04 TM03 TM02 0 0 8 8 TMOD0 Modulo register (8)
TOE0 TO enable flag
P20 output latch
PORT2.0 PGMB bit 2 Port 2 input/output mode To serial interface
8 TOUT0 Comparator (8) 8 Reset T0 Count register (8) CP Clear INTT0 IRQT0 set signal Match TOUT F/F Output buffer PTO0/P20
Timer operation start RESET IRQT0 clear signal
PD753012, 753016, 753017
To timer/event counter (channel 2)
Note Instruction execution Caution When setting data to the TM0, be sure to set bits 0 and 1 to 0.
Figure 6-7. Timer/Event Counter Block Diagram (channel 1)
Internal bus 8 TM1 - TM16 TM15 TM14 TM13 TM12 TM11 TM10 Decoder 8 TMOD1 PORT1.2 Modulo register (8) 8 Input buffer TI1/TI2/P12/INT2
Timer/event counter output (channel 2)
TOE1 T1 enable flag
PORT2.1 P21 output latch
PMGB.2
Port 2 input/output mode
Comparator (8) 8 MPX CP Count register (8) Clear T1
Match
TOUT F/F Reset
P21/PTO1 Output buffer
fx/25 fx/26 From clock fx/28 generator fx/210 fx/212
RESET Timer operation start 16 bit timer/event counter mode Selector
PD753012, 753016, 753017
IRQT1 clear signal
Timer/event counter match signal (channel 2) (When 16-bit timer/event counter mode)
Timer/event counter reload signal (channel 2)
INTT1 IRQT1 set signal
Timer/event counter comparator (channel 2) (When 16-bit timer/event counter mode)
29
Selector
Selector
TI1/TI2/ P12/INT2 From clock generator
fx fx/2 fx/24 fx/26 fx/28 fx/210
MPX
CP
T2 Count register (8) Clear
8
Reset Overflow Carrier generator mode
Selector
30
8 TM2
TM26 TM25 TM24 TM23 TM22 TM21 TM20
Figure 6-8. Timer/Event Counter Block Diagram (channel 2)
Internal bus 8 TMOD2H
Modulo register for high level period setup (8)
8 TMOD2
TGCE
8 TC2
TOE2 REMC NRZB NRZ
Reload
PORT1.2 Decoder
8
Modulo register (8) 8
PORT2.2 PMGB.2 P22 Port 2 output latch input/output
P22/PCL/PTO2
MPX (8) 8 Comparator (8)
Match
Iuput buffer
TOUT F/F
Output buffer
Timer/event counter clock input (channel 1)
16-bit timer/event counter mode
INTT2 IRQT2 set signal IRQT2 clear signal
Timer operation start
RESET Timer event counter TOUT F/F (channel 0)
Timer/event counter clear signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When carrier generator mode) From clock output circuit
PD753012, 753016, 753017
PD753012, 753016, 753017
6.8 Serial Interface
The PD753017 is provided with an 8-bit clocked serial interface. This serial interface operates in the following four modes: * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode * SBI mode
31
ACKE
P02/SO/SB0
Selector Bus release/ command/ acknowledge detector RELD CMDD ACKD
Busy/ acknowledge output circuit
BSYE
ACKT
32
8/4 Bit test CSIM P03/SI/SB1 Selector P01/SCK P01 output Iatch
Figure 6-9. Serial Interface Block Diagram
Internal bus 8 8 8 Bit manipulation SBIC RELT CMDT (8) SET CLR Shift register (SIO) (8) D Q SO latch Bit test
Slave address register (SVA) (8) Match signal Address comparator
PD753012, 753016, 753017
INTCSI Serial clock counter INTCSI control circuit IRQCSI set signal fX/23 fX/24 fX/26 TOUT F/F (from timer/event counter)
Serial clock control circuit
Serial clock selector
External SCK
PD753012, 753016, 753017
6.9 LCD Controller/Driver
The PD753017 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the LCD panel directly. The PD753017 LCD controller/driver functions are as follows: * Display data memory is read automatically by DMA operation and segment and common signals are generated. * Display mode can be selected from among the following five: <1> Static <2> 1/2 duty (time multiplexing by 2), 1/2 bias <3> 1/3 duty (time multiplexing by 3), 1/2 bias <4> 1/3 duty (time multiplexing by 3), 1/3 bias <5> 1/4 duty (time multiplexing by 4), 1/3 bias * A frame frequency can be selected from among four in each display mode. * A maximum of 32 segment signal output pins (S0-S31) and four common signal output pins (COM0-COM3). * The segment signal output pins (S24-S27 and S28-S31) can be changed to the output ports in 4-pin units. * Split-resistor can be incorporated to supply LCD drive power. (Mask option) * Various bias methods and LCD drive voltages can be applicable. * When display is off, current flow to the split resistor is cut. * Display data memory not used for display can be used for normal data memory. * It can also operate by using the subsystem clock.
33
Segment driver
Common driver
LCD drive voltage control
S31/BP7
S30/BP6
S24/BP0
S23
S0
COM3 COM2 COM1 COM0
VLC2
VLC1
VLC0
LCD drive mode changer
34
4 Display data memory 1FFH 32 10 1FEH 32 10 1F9H 32 10 32 10 32 10 32 10 Multiplexer Selector
Figure 6-10. LCD Controller/Driver Block Diagram
Internal bus 8 1F8H 32 10 1E0H 32 10 4
Display control register
4 Port 3 output latch 10
8
Port mode register group A
Display mode register
10
32 10
32 10
Timing controller
fLCD
PD753012, 753016, 753017
P31/ P30/ SYNC LCDCL
PD753012, 753016, 753017
6.10 Bit Sequential Buffer ... 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-11. Bit Sequential Buffer Format
Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 0 3 FC1H 2 1 0 3 FC0H 2 1 0
BSB3
BSB2
BSB1
BSB0
L register
L = FH
L = CH L = BH
L = 8H L = 7H
L = 4H L = 3H DECS L
L = 0H
INCS L
Remarks 1. 2.
In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification.
35
PD753012, 753016, 753017
7. INTERRUPT FUNCTION AND TEST FUNCTION
PD753017 has eight types of interrupt sources and two types of test sources. Among the test sources, INT2
is provided with two testable inputs for edge detection.
PD753017 has the following functions in the interrupt controller.
(1) Interrupt function * Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IEXXX) and interrupt master enable flag (IME). * Can set any interrupt start address. * Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). * Test function of interrupt request flag (IRQXXX). An interrupt generated can be checked by software. * Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function * Test request flag (IRQXXX) generation can be checked by software. * Release the standby mode. The test source to be released can be selected by the test enable flag.
36
Figure 7-1. Interrupt Control Circuit Block Diagram
Internal bus 2 1 4 IME IPS IM2 IM1 IM0 Interruput enable flag (IExxx) Decoder INTBT INT4/P00 INT0/P10 INT1/P11
Note
Selector
IST1
IST0
IRQBT
VRQn
Both edge detector Edge detector Edge detector INTCSI INTT0 INTT1 INTT2 INTW
IRQ4 IRQ0 IRQ1 IRQCSI IRQT0 IRQT1 IRQT2 IRQW IRQ2 Standby release signal Priority control circuit Vector table address generator
PD753012, 753016, 753017
INT2/TI1/TI2/P12
Rising edge detector
Selector
KR0/P60 KR3/P63
Falling edge detector
IM2
Note Noise eliminator (Standby release is disabled when noise eliminator is selected.)
37
PD753012, 753016, 753017
8. STANDBY FUNCTION
In order to save power consumption while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD753017. Table 8-1. Operation Status in Standby Mode
STOP Mode Set instruction System clock when set STOP instruction Settable only when the main system clock is used. Only the main system clock stops oscillation. Operation stops HALT Mode HALT instruction Settable both by the main system clock and subsystem clock. Only the CPU halts (oscillation continues). Operation. Note 1 BT mode : Sets IRQBT at reference time intervals. WT mode: Generates reset signal when BT overflows. Operable Operable
Note 1
Operation status
Clock generator
Basic interval timer
Serial interface Timer/event counter
Operable only when an external SCK input is selected as the serial clock. Operable only when a signal input to the TI0-TI2 pins is specified as the count clock.
Note 1
Watch timer
Operable when fXT is selected as the count clock. Operable only when fXT is selected as the LCDCL. The INT1, 2, and 4 are operable. Only the INT0 is not operated.Note 2 The operation stops.
Operable
LCD controller/driver
Operable
External interrupt
CPU Release signal
Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag or RESET signal input.
Notes 1. 2.
Cannot operate only when the main system clock stops. Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register(IM0).
38
PD753012, 753016, 753017
9. RESET FUNCTION
There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/ watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 91 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function
RESET
Internal reset signal
Reset signal sent from the basic interval timer/watchdog timer WDTM
Internal bus
The PD753017 is set by the RESET signal generated and each device is initialized as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation
Wait Note
RESET signal generated Operation mode or standby mode HALT mode Internal reset operation Operation mode
Note
The following two times can be selected by the mask option. 2 17/fX (21.8 ms : at 6.00 MHz operation, 31.3 ms : at 4.19 MHz operation) 2 15/fX (5.46 ms : at 6.00 MHz operation, 7.81 ms : at 4.19 MHz operation)
39
PD753012, 753016, 753017
Table 9-1. Status of Each Device After Reset (1/2)
RESET Signal Generation in Standby Mode RESET Signal Generation in Operation Sets the low-order 6 bits of program memory's address 0000H to the PC13-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 7 bits of program memory's address 0000H to the PC14-PC8 and the contents of address 0001H to the PC7-PC0. Undefined 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH
Hardware Program counter (PC)
PD753012, 753016
Sets the low-order 6 bits of program memory's address 0000H to the PC13-PC8 and the contents of address 0001H to the PC7-PC0. Sets the low-order 7 bits of program memory's address 0000H to the PC14-PC8 and the contents of address 0001H to the PC7-PC0. Held 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH
PD753017
PSW
Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0) Bank enable flag (MBE, RBE)
Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) General-purpose register (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Basic interval/ watchdog timer Timer/event counter (T0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer/event counter (T1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer/event counter (T2) Counter (T2) Modulo register (TMOD2) High level period setting modulo register (TMOD2H) Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB TGCE Watch timer Mode register (WM)
0 0, 0 0, 0, 0 0 0
0 0, 0 0, 0, 0 0 0
40
PD753012, 753016, 753017
Table 9-1. Status of Each Device After Reset (2/2)
RESET Signal Generation in Standby Mode Held 0 0 Held 0 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 0 Off Cleared (0) 0 0 Held RESET Signal Generation in Operation Undefined 0 0 Undefined 0 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 0 Off Cleared (0) 0 0 Undefined
Hardware Serial interface Shift register (SIO) Operating mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) Clock generator, clock output circuit Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM)
Sub-oscillator control register (SOS) LCD controller /driver Interrupt function Display mode register (LCDM) Display control register (LCDC) Interrupt request flag (IRQXXX) Interrupt enable flag (IEXXX) Interrupt master enable flag (IME) INT0, 1, 2 mode registers (IM0, IM1, IM2) Priority selection register (IPS) Digital port Output buffer Output latch I/O mode registers (PMGA, PMGB) Pull-up resistor setting register (POGA) Bit sequential buffer (BSB0-BSB3)
41
PD753012, 753016, 753017
10. MASK OPTION
The PD753017 has the following mask options. * Mask option of P40 to P43 and P50 to P53 An on-chip pull-up resistor can be selected. <1> Specifies an on-chip pull-up resistor in bit units. <2> Does not specify an on-chip pull-up resistor. * Mask option of VLC0 to VLC2 and BIAS pins An on-chip split resistor for LDC driving can be selected. <1> Does not specify an on-chip divider resistor <2> Specifies four 10-k (typ.) on-chip split resistors at the same time. <3> Specifies four 100-k (typ.) on-chip split resistors at the same time. * Standby function mask option Wait time can be selected by RESET signai input. <1> 2 17/fX (21.8 ms: at fX = 6.0 MHz, 31.3 ms: at fX = 4.19 MHz) <2> 2 15/fX (5.46 ms: at fX = 6.0 MHz, 7.81 ms: at fX = 4.19 MHz) * Subsystem clock mask option Selectable an on-chip feedback resistor can be used/cannot be used <1> Make an on-chip feedback resistor usable (Switch on-chip feedback resistor ON/OFF in software) <2> Make an on-chip feedback resistor unusable (Disconnects on-chip feedback resistor in hardware)
42
PD753012, 753016, 753017
11. INSTRUCTION SETS AND THEIR OPERATIONS
(1) Operand identifiers and methods of use Operands are written in the operand column of each instruction in accordance with the method of use for the operand identifier of the instruction. For details, refer to RA75X Assembler Package User's Manual-- Language (U12385E). If there are several elements, one of them is selected. Capital letters and the + and - symbols are key words and are written as they are. For immediate data, appropriate numbers and labels are written. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be written. However, there are restrictions in the labels that can be written for fmem and pmem. For details, refer to User's Manual.
Identifier reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IEXXX RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, BC, XA, BC, BC, DE, DE BC, DE, DE, HL HL DE, HL, XA', BC', DE', HL' HL, XA', BC', DE', HL' Format
HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label
Note
FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-2FFFH immediate data or label (PD753012) 0000H-3FFFH immediate data or label (PD753016, 753017) 0000H-5FFFH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (where bit 0 = 0) or label PORT0-PORT7 IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW RB0-RB3 MB0, MB1, MB2, MB3, MB15
Note mem can be only used even address in 8-bit data processing.
43
PD753012, 753016, 753017
(2) Legend in explanation of operation A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IEXXX RBS MBS PCC . (XX) XXH : A register, 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair : XA' expanded register pair : BC' expanded register pair : DE' expanded register pair : HL' expanded register pair : Program counter : Stack pointer : Carry flag, bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Port n (n = 0-7) : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Separation between address and bit : The contents addressed by XX : Hexadecimal data
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PD753012, 753016, 753017
(3) Explanation of symbols under addressing area column
*1 MB = MBE*MBS (MBS = 0-3, 15) MB = 0 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0-3, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH
*2 *3
Data memory addressing
*4 *5 *6
PD753012 PD753016 753017
addr = 0000H-2FFFH addr = 0000H-3FFFH
*7
PD753012 753016 753017 (In Mk I mode) PD753017 (In Mk II mode)
addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16
addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 caddr = 0000H-0FFFH(PC13, 12 = 00B) or 1000H-1FFFH(PC13, 12 = 01B) or 2000H-2FFFH(PC13, 12 = 10B) caddr = 0000H-0FFFH(PC13, 12 1000H-1FFFH(PC13, 12 2000H-2FFFH(PC13, 12 3000H-3FFFH(PC13, 12 = = = = 00B) or 01B) or 10B) or 11B) = = = = = = 000B) 001B) 010B) 011B) 100B) 101B) or or or or or Program memory addressing
*8
PD753012
PD753016
PD753017
caddr = 0000H-0FFFH(PC14, 13, 12 1000H-1FFFH(PC14, 13, 12 2000H-2FFFH(PC14, 13, 12 3000H-3FFFH(PC14, 13, 12 4000H-4FFFH(PC14, 13, 12 5000H-5FFFH(PC14, 13, 12
*9 *10 *11
faddr = 0000H-07FFH taddr = 0020H-007FH
PD753012 PD753016 PD753017
addr1 = 0000H-2FFFH addr1 = 0000H-3FFFH addr1 = 0000H-5FFFH
Remarks 1. 2. 3. 4.
MB indicates memory bank that can be accessed. In *2, MB = 0 independently of how MBE and MBS are set. In *4 and *5, MB = 15 independently of how MBE and MBS are set. *6 to *11 indicate the areas that can be addressed.
45
PD753012, 753016, 753017
(4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. * When no skip is made: S = 0 * When the skipped instruction is a 1- or 2-byte instruction: S = 1 * When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC.
46
PD753012, 753016, 753017
Number of Machine Cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String effect A String effect B
Instruction Group Transfer instruction
Mnemonic
Operand
Number of Bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2
Operation
Addressing Area
Skip Condition
MOV
A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA
String effect A
XCH
A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'
47
PD753012, 753016, 753017
Number of Machine Cycles 3
Instruction Group Table
Mnemonic
Operand
Number of Bytes 1
Operation XA (PC13-8+DE)ROM
* PD753017 XA (PC14-8+DE)ROM
Addressing Area
Skip Condition
MOVTNote 1
XA, @PCDE
XA, @PCXA
1
3
XA (PC13-8+XA)ROM
* PD753017 XA (PC14-8+XA)ROM
XA, @BCDENote 2
1
3
XA (B1,0+CDE)ROM
* PD753017 XA (B2-0+CDE)ROM
*6 *11
XA, @BCXANote 2
1
3
XA (B1,0+CXA)ROM
*
*6 *11
PD753017 XA (B2-0+CXA)ROM
Bit transfer
MOV1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY
2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2
2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2
CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A, CY A+(HL)+CY XA, CY XA+rp'+CY rp'1, CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A, CY A-(HL)-CY XA, CY XA-rp'-CY rp'1, CY rp'1-XA-CY
*4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1
Operation
ADDS
A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA
ADDC
A, @HL XA, rp' rp'1, XA
SUBS
A, @HL XA, rp' rp'1, XA
*1
borrow borrow borrow
SUBC
A, @HL XA, rp' rp'1, XA
*1
Notes 1. 2.
The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Only the following bits are valid for the B register.
PD753012, 753016 : low-order 2 bits PD753017
: low-order 3 bits
Remark PC14 is fixed to 0 when the PD753017 is set in the Mk I mode.
48
PD753012, 753016, 753017
Number of Machine Cycles 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA CY A0, A3 CY, An-1 An AA reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY CY=1 *1 *1 *1 *1 *3 reg=0 rp1=00H (HL)=0 (mem)=0 reg=FH rp'=FFH reg=n4 (HL) = n4 A = (HL) XA = (HL) A=reg XA=rp' *1 *1 *1
Instruction Group Operating instructions
Mnemonic
Operand
Number of Bytes 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1
Operation
Addressing Area
Skip Condition
AND
A, #n4 A, @HL XA, rp' rp'1, XA
OR
A, #n4 A, @HL XA, rp' rp'1, XA
XOR
A, #n4 A, @HL XA, rp' rp'1, XA
Accumulator manipulation instructions Increment and Decrement instructions
RORC NOT INCS
A A reg rp1 @HL mem
DECS
reg rp'
Comparison instruction
SKE
reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp'
Carry flag manipulation instruction
SET1 CLR1 SKT NOT1
CY CY CY CY
49
PD753012, 753016, 753017
Number of Machine Cycles 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit)=1 Skip if (fmem.bit)=1 Skip if (pmem7-2+L3-2.bit(L1-0))=1 Skip if (H+mem3-0.bit)=1 Skip if (mem.bit)=0 Skip if (fmem.bit)=0 Skip if (pmem7-2+L3-2.bit(L1-0))=0 Skip if (H+mem3-0.bit)=0 Skip if (fmem.bit)=1 and clear Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if (H+mem3-0.bit)=1 and clear CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit)
Instruction Group Memory bit manipulation instructions
Mnemonic
Operand
Number of Bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Operation
Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1
Skip Condition
SET1
mem.bit fmem.bit pmem.@L @H+mem.bit
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
(mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR
fmem.bit pmem.@L @H+mem.bit
AND1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
OR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
XOR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
50
PD753012, 753016, 753017
Number of Machine Cycles -
Instruction Group Branch instructions
Mnemonic
Operand
Number of Bytes -
Operation PC13-0 addr Select appropriate instruction from among BR !addr, BRCB !caddr, and BR $addr according to the assembler being used. BR !addr BRCB !caddr BR $addr
*
Addressing Area *6
Skip Condition
BRNote 1
addr
addr1
-
-
PD753017 PC14-0 addr1 Select appropriate instruction from among BR !addr, BRA !caddr1 BRCB !caddr, and BR $addr according to the assembler being used. BR !addr BRA !addr1 BRCB !caddr BR $addr
*11
!addr
3
3
PC13-0 addr
*
*6
PD753017 PC14 0, PC13-0 addr
*7
$addr $addr1
1 1
2 2
PC13-0 addr
*
PD753017 PC14-0 addr1
PCDE
2
3
PC13-0 PC13-8+DE
*
PD753017 PC14-0 PC14-8+DE
PC13-0 PC13-8+XA
PCXA
2
3
*
PD753017 PC14-0 PC14-8+XA
*6 *11
BCDENote 2
2
3
PC13-0 B1,0+CDE
*
PD753017 PC14-0 B2-0+CDE
BCXANote2
2
3
PC13-0 B1,0+CXA
*
*6 *11
PD753017 PC14-0 B2-0+CXA PD753012, 753016 PC13-0 addr PD753017 PC14-0 addr1
BRANote1
!addr
3
3
*
*6
!addr1
3
3
*
*11
Notes 1. 2.
The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Only the following bits are valid for the B register.
PD753012, 753016 : low-order 2 bits PD753017
: low-order 3 bits
Remark PC14 is fixed to 0 when the PD753017 is set in the Mk I mode.
51
PD753012, 753016, 753017
Number of Machine Cycles 2
Instruction Group Branch instructions
Mnemonic
Operand
Number of Bytes 2
Operation PC13-0 PC13,12+caddr11-0
*
Addressing Area *8
Skip Condition
BRCBNote
!caddr
PD753017 PC14-0 PC14,13,12+caddr11-0
*6
Subroutine stack control instructions
CALLANote
!addr
3
3
* PD753012, 753016 (SP-5)(SP-6)(SP-3)(SP-4) 0, 0, PC13-0 (SP-2) x, x, MBE, RBE PC13-0 addr, SP SP-6
!addr1
3
3
PD753017 (SP-5)(SP-6)(SP-3)(SP-4) 0, PC14-0 (SP-2) x, x, MBE, RBE PC14-0 addr1, SP SP-6
*
*11
CALLNote
!addr
3
3
(SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 addr, SP SP-4
*6
4
PD753012, 753016 (SP-5)(SP-6)(SP-3)(SP-4) 0, 0, PC13-0 (SP-2) x, x, MBE, RBE PC13-0 addr, SP SP-6
*
4
PD753017 (SP-5)(SP-6)(SP-3)(SP-4) 0, PC14-0 (SP-2) x, x, MBE, RBE PC14 0, PC13-0 addr, SP SP-6
*
CALLFNote
!faddr
2
2
(SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 000+faddr, SP SP-4
*9
3
PD753012, 753016 (SP-5)(SP-6)(SP-3)(SP-4) 0, 0, PC13-0 (SP-2) x, x, MBE, RBE PC13-0 000+faddr, SP SP-6
*
3
PD753017 (SP-5)(SP-6)(SP-3)(SP-4) 0, PC14-0 (SP-2) x, x, MBE, RBE PC14-0 0000+faddr, SP SP-6
*
Note
The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
Remark PC14 is fixed to 0 when the PD753017 is set in the Mk I mode.
52
PD753012, 753016, 753017
Number of Machine Cycles 3
Instruction Group Subroutine stack control instructions
Mnemonic
Operand
Number of Bytes 1
Operation MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+4
Addressing Area
Skip Condition
RETNote
PD753012, 753016 x, x, MBE, RBE (SP+4) 0, 0, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+6
*
PD753017 x, x, MBE, RBE (SP+4) 0, PC14, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+6
*
RETSNote
1
3+S
MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+4 then skip unconditionally
Unconditional
PD753012, 753016 x, x, MBE, RBE (SP+4) 0, 0, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+6 then skip unconditionally
*
PD753017 x, x, MBE, RBE (SP+4) 0, PC14, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+6 then skip unconditionally
*
RETINote
1
3
MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6
PD753012, 753016 0, 0, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6
*
PD753017 0, PC14, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6
*
Note
The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
Remark PC14 is fixed to 0 when the PD753017 is set in the Mk I mode.
53
PD753012, 753016, 753017
Number of Machine Cycles 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3
Instruction Group Subroutine stack control instructions
Mnemonic
Operand
Number of Bytes 1 2 1 2 2
Operation (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1)(SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 IME(IPS.3) 1 IEXXX 1 IME(IPS.3) 0 IEXXX 0 A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA Set HALT mode (PCC.2 1) Set STOP mode (PCC.3 1) No operation RBS n MBS n (n = 0-3) (n = 0-3, 15) (n = 0-7) (n = 4, 6) (n = 2-7) (n = 4, 6)
Addressing Area
Skip Condition
PUSH
rp BS
POP
rp BS
Interrupt control instructions
EI IEXXX DI IEXXX
2 2 2 2 2 2 2 2 2 1
Input/output instructions
INNote 1
A, PORTn XA, PORTn
OUTNote 1
PORTn, A PORTn, XA
CPU control instruction
HALT STOP NOP
Special instruction
SEL
RBn MBn
2 2 1
GETINotes 2, 3
taddr
* When TBR instruction PC13-0 (taddr)5-0+(taddr+1)
----------------------------------
*10
------------
* When TCALL instruction (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 (taddr)5-0+(taddr+1) SP SP-4
---------------------------------- ------------
* When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed 1 3 * PD753017 * When TBR instruction PC13-0 (taddr)5-0+(taddr+1) PC14 0
Depending on the reference instruction
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - -
------------
4
* When TCALL instruction (SP-5)(SP-6)(SP-3)(SP-4) 0, PC14-0 (SP-2) x, x, MBE, RBE PC13-0 (taddr)5-0+(taddr+1) SP SP-6, PC14 0
-------------
------------------------------------------
3
* When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed
Depending on the reference instruction
Notes 1. 2. 3.
While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. The shaded area is applicable only to the Mk II mode. The other area is applicable only to Mk I mode. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction.
Remark PC14 is fixed to 0 when the PD753017 is set in the Mk I mode.
54
PD753012, 753016, 753017
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Other than ports 4 and 5 Ports 4 and 5 Output voltage High-level output current VO IOH Per pin Total of all pins Low-level output current IOL Per pin Total of all pins Operating ambient temperature Storage temperature TA Tstg Pull-up resistor provided N-ch open drain Conditions Ratings -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to +14 -0.3 to VDD +0.3 -10 -30 30 200 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA C C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Capacitance (TA = 25 C, VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Pins other than tested pins: 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
55
PD753012, 753016, 753017
Main System Clock Oscillator Characteristics (TA = -40 to +85 C)
Recommended Constants
Oscillator Ceramic oscillator
Parameter Oscillation frequency (fX) Note 1
Conditions VDD = 2.2 to 5.5 V
MIN. 1.0
TYP.
MAX. 6.0Note 2
Unit MHz
X1
X2 Oscillation stabilization timeNote 3 After VDD has reached MIN. value of oscillation voltage range VDD = 2.2 to 5.5 V 1.0 4 ms
C1 VDD Crystal oscillator X1 X2
C2
Oscillation frequency (fX) Note 1
6.0Note 2
MHz
C1 VDD External clock
C2
Oscillation stabilization timeNote 3
VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V
10 30 1.0 6.0Note 4
ms
X1
X2
X1 input frequency (fX) Note 1
VDD = 1.8 to 5.5 V
MHz
X1 input high-, low-level widths (tXH, tXL)
VDD = 1.8 to 5.5 V
83.3
500
ns
Notes 1. 2.
The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. When the oscillation frequency is 4.7 MHz < fX 6.0 MHz at 2.2 V VDD < 2.7 V, assign a value other than 0011 to the processor clock control register (PCC). If 0011 is assigned to PCC, one machine cycle falls short of the rated value of 0.85 s.
3. 4.
The oscillation stabilization time is the time required for oscillation to stabilize after VDD has been applied or STOP mode has been released. When the X1 input frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, assign a value other than 0011 to the processor clock control register (PCC). If 0011 is assigned to PCC, one machine cycle falls short of the rated value of 0.95 s.
Caution When using the main system clock oscillator, wire the portion enclosed by the dotted line in the above figure as follows to prevent adverse influence from wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with any other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract any signal from the oscillator.
56
PD753012, 753016, 753017
Subsystem Clock Oscillator Characteristics (TA = -40 to +85 C)
Recommended Constants
Oscillator Crystal oscillator
Parameter Oscillation frequency (fXT)Note 1
Conditions VDD = 2.2 to 5.5 V
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
XT1
XT2 R
C3 VDD
External clock
C4
Oscillation stabilization timeNote 2
VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V
1.0
2 10
s
XT1
XT2
XT1 input frequency (fXT)Note 1
VDD = 1.8 to 5.5 V
32
100
kHz
XT1 input high-, low-level widths (tXTH, tXTL)
VDD = 1.8 to 5.5 V
5
15
s
Notes 1. 2.
The oscillation frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied.
Caution When using the subsystem clock oscillator, wire the portion enclosed by the dotted line in the above figure as follows to prevent adverse influence from to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with any other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract any signal from the oscillator. The subsystem clock oscillator has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillator. Therefore, exercise utmost care in wiring the subsystem clock oscillator.
57
PD753012, 753016, 753017
Recommended Oscillator Constants Ceramic oscillator (TA = -40 to +85 C)
Recommended Circuit Constant (pF) C1 Murata Mfg. Co., Ltd. CSB1000JNote CSA2.00MG040 CST2.00MG040 CSA4.19MG CST4.19MGW CSA4.19MGU CST4.19MGWU CSA6.00MG CST6.00MGW CSA6.00MGU CST6.00MGWU Kyocera Corp. KBR-1000F/Y KBR-2.0MS KBR-4.19MSA KBR-4.19MKS PBRC 4.19A PBRC 4.19B KBR-6.0MSA KBR-6.0MKS PBRC 6.00A PBRC 6.00B TDK Corp. FCR2.0MC3 FCR4.19MC5 FCR6.0MC5 2.0 4.19 6.0 - - 30 - - 30 2.0 2.5 2.7 5.5 5.5 5.5 Capacitor-contained model -20 to +85 C 6.0 - - 33 - - 33 2.8 5.5 Capacitor-contained model -20 to +85 C -20 to +85 C 1.0 2.0 4.19 6.0 4.19 1.0 2.0 100 100 - 30 - 30 - 30 - 30 - 220 82 33 C2 100 100 - 30 - 30 - 30 - 30 - 220 82 33 2.9 3.1 2.7 5.5 5.5 5.5 2.5 5.5 Capacitor-contained model -20 to +85 C 2.7 5.5 Capacitor-contained model 2.2 5.5 Capacitor-contained model 2.5 5.5 Capacitor-contained model Capacitor-contained model Oscillation Voltage Range (VDD) MIN. 2.7 MAX. 5.5 Rd = 5.6 k
Manufacturer
Part Number
Frequency (MHz)
Remark
Note
When using the CSB1000J (1.00 MHz) by Murata Mfg. Co., Ltd. as a ceramic oscillator, a limiting resistor (Rd = 5.6 k) is necessary (refer to the figure below). The resistor is not necessary when using the other recommended oscillators.
Example of recommended main system clock oscillator (when using CSB1000J by Murata Mfg. Co., Ltd.)
X1 CSB1000J C1 VDD
X2 Rd C2
58
PD753012, 753016, 753017
DC Characteristics (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter Low-level output current High-level input voltage VIH2 Ports 0, 1, 6, 7, RESET VIH1 Symbol IOL Per pin Total of all pins Ports 2, 3 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V VIH3 Ports 4, 5 Pull-up resistor provided N-ch open drain 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V VIH4 Low-level input voltage VIL2 Ports 0, 1, 6, 7, RESET VIL1 X1, XT1 Ports 2, 3, 4, 5 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V VIL3 High-level output voltage Low-level output voltage VOH VOL1 X1, XT1 SCK, SO, ports 0, 2, 3, 6, 7, BP0 to 7 IOH = -1 mA SCK, SO, ports 0, 2, 3, 4, 5, 6, 7, BP0 to 7 IOL = 15 mA VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 SB0, 1 N-ch open drain Pull-up resistor 1 k High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 ILIL3 VIN = 13 V VIN = 0 V VIN = VDD Pins other than X1, XT1 X1, XT1 Ports 4, 5 (N-ch open drain) Pins other than X1, XT1, ports 4 and 5 X1, XT1 Ports 4, 5 (N-ch open drain) When input instruction is not executed Ports 4, 5 (N-ch open drain) When input instruction is executed High-level output ILOH1 VOUT = VDD -30 VDD = 5 V VDD = 3 V -10 -3 -27 -8 3 3 20 20 -3 -20 -3 0.4 0.2 VDD V V 0.7 VDD 0.9 VDD 0.8 VDD 0.9 VDD 0.7 VDD 0.9 VDD 0.7 VDD 0.9 VDD VDD - 0.1 0 0 0 0 0 VDD - 0.5 0.2 2.0 Conditions MIN. TYP. MAX. 15 120 VDD VDD VDD VDD VDD VDD 13 13 VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.1 Unit mA mA V V V V V V V V V V V V V V V V
A A A A A A A A A A
SCK, SO/SB0, SB1, ports 2, 3, 6, 7, ports 4, 5 (with on-chip pull-up resistor), BP0 to 7
leakage current Low-level output leakage current Internal pull-up resistor
ILOH2 ILOL
VOUT = 13 V Ports 4, 5 (N-ch open drain) VOUT = 0 V
20 -3
A A
k k
RL1 RL2
VIN = 0 V
Ports 0, 1, 2, 3, 6, 7 (except P00 pin) Ports 4, 5 (mask option)
50 15
100 30
200 60
59
PD753012, 753016, 753017
DC Characteristics (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter LCD drive voltage LCD divider resistorNote 1 LCD output voltage deviationNote 2 (common) LCD output voltage deviationNote 2 (segment) Supply currentNote 3 IDD1
6.00 MHzNote 4 crystal oscillation C1 = C2 = 22 pF 4.19 MHzNote 4 crystal oscillation C1 = C2 = 22 pF
Symbol VLCD RLCD1 RLCD2 VODC IO = 5A
Conditions
MIN. 2.2 50 5
TYP.
MAX. VDD
Unit V k k V
100 10
200 20 0.2
VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3
0
VODS
IO = 1A
2.2 V VLCD VDD
0
0.2
V
VDD = 5.0 V 10 %Note 5 VDD = 3.0 V 10 HALT mode %Note 6 VDD = 5.0 V 10 % VDD = 3.0 V 10 %
1.9 0.4 0.72 0.27 1.5 0.25 0.7 0.23 12 4.5 12 6 6 8.5 3 8.5 3.5 3.5 0.05 0.02
6.0 1.3 2.1 0.8 4.0 0.75 2.0 0.7 35 12 24 18 12 25 9 17 12 7 10 5 3
mA mA mA mA mA mA mA mA
IDD2
IDD1
VDD = 5.0 V 10 %Note 5 VDD = 3.0 V 10 %Note 6 HALT mode Lowvoltage modeNote 8
Low current dissipation mode Note 9
IDD2
VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 3.0 V 10 % VDD = 2.5 V 10 % VDD = 3.0 V, TA = 25 C VDD = 3.0 V 10 % VDD = 3.0 V, TA = 25 C Lowvoltage modeNote 8
Low power dissipation mode Note 9
IDD3
32.768 kHz Note 7 crystal oscillation
A A A A A A A A A A A A A
IDD4
HALT mode
VDD = 3.0 V 10 % VDD = 2.5 V 10 % VDD = 3.0 V, TA = 25 C VDD = 3.0 V 10 % VDD = 3.0 V, TA = 25 C
IDD5
XT1 = 0 V STOP modeNote 10
VDD = 5.0 V 10 % VDD = 3.0 V 10 % TA = 25 C
0.02
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9.
Either RLCD1 or RLCD2 can be selected by mask option. Voltage deviation is the difference between the ideal values (VLCDn; n = 0, 1, 2) of the segment and common outputs and the output voltage. The current flowing through the internal pull-up resistor and the LCD split resistor is not included. Including the case when the subsystem clock oscillates. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. When the device operates in low-speed mode with PCC set to 0000. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. When 0000 is assigned to the sub-oscillator control register (SOS). When 0010 is assigned to the SOS.
10. When the sub-oscillator feedback resistor is not used with the SOS set to 00X1 (X: don't care).
60
PD753012, 753016, 753017
AC Characteristics (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter CPU clock cycle timeNote 1 Symbol tCY Conditions When using VDD = 2.7 to 5.5 V Operates ceramic or with main crystal When using VDD = 2.7 to 5.5 V system external clock VDD = 1.8 to 5.5 V clock Operates with subsystem clock TI0, TI1, TI2 input frequency fTI VDD = 2.7 to 5.5 V MIN. 0.67 0.85 0.67 0.95 114 0 0 TI0, TI1, TI2 high-, low-level widths Interrupt input high-, low-level widths INT1, 2, 4 KR0-7 RESET low-level width tRSL tINTH, tINTL INT0 IM02 = 0 IM02 = 1 tTIH, tTIL VDD = 2.7 to 5.5 V 0.48 1.8 Note 2 10 10 10 10 122 TYP. MAX. 64 64 64 64 125 1 275 Unit
s s s s s
MHz kHz
(minimum instruction execution time = 1 machine cycle)
s s s s s s s
Notes 1.
The cycle time of the CPU clock () is determined by the oscillation frequency of the connected oscillator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage VDD vs. cycle time tCY charwith the main system clock.
Cycle time tCY [ s]
6 5 Operation guaranteed range 4 3 64 60 70 tCY vs VDD (with main system clock)
acteristics when the device operates 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0).
2
1 0.95 0.85 0.67 0.5
0
1
2 3 1.8 2.2 2.7
4
5 5.5 6
Supply voltage VDD [V]
Remark The shaded portion is guaranteed only when using the external clock.
61
PD753012, 753016, 753017
Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK *** internal clock output): (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level widths SI Note 1 setup time (vs. SCK ) tKL1, tKH1 tSIK1 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKCY1/2-50 tKCY1/2-150 150 500 SI Note 1hold time (vs. SCK ) SCK SO Note 1 output delay time tKSI1 VDD = 2.7 to 5.5 V RL = 1 kNote 2 CL = 100 pF 400 600 tKSO1 VDD = 2.7 to 5.5 V 0 0 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Notes 1. 2.
Replace the parameter with SB0 or SB1 in the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.
2-wire and 3-wire serial I/O modes (SCK *** external clock input): (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level widths SI Note 1 setup time (vs. SCK ) SI Note 1 hold time (vs. SCK ) SCK SO Note 1 output delay time tKL2, tKH2 tSIK2 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 400 1600 100 150 tKSI2 VDD = 2.7 to 5.5 V RL = 1 kNote 2 CL = 100 pF 400 600 tKSO2 VDD = 2.7 to 5.5 V 0 0 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Notes 1. 2.
Replace the parameter with SB0 or SB1 in the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.
62
PD753012, 753016, 753017
SBI mode (SCK *** internal clock output (master)): (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level widths tKL3, tKH3 SB0, 1 setup time (vs. SCK ) SB0, 1 hold time (vs. SCK ) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI3 tKSO3 RL = 1 kNote CL = 100 pF VDD = 2.7 to 5.5 V tSIK3 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKCY3/2-50 tKCY3/2-150 150 500 tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.
SBI mode (SCK *** external clock input (slave)): (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level widths tKL4, tKH4 SB0, 1 setup time (vs. SCK ) SB0, 1 hold time (vs. SCK ) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI4 tKSO4 RL = 1 kNote CL = 100 pF VDD = 2.7 to 5.5 V tSIK4 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 400 1600 100 150 tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.
63
PD753012, 753016, 753017
AC timing test points (except X1 and XT1 inputs)
VIH (MIN.) VIL (MAX.)
VIH (MIN.) VIL (MAX.)
VOH (MIN.) VOL (MAX.)
VOH (MIN.) VOL (MAX.)
Clock timing
1/fX tXL tXH VDD - 0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD - 0.1 V XT1 input 0.1 V
TI0, TI1, TI2 timing
1/fTI tTIL tTIH
TI0, TI1, TI2
64
PD753012, 753016, 753017
Serial transfer timing 3-wire serial I/O mode
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKSO1
SO
Output data
2-wire serial I/O mode
tKCY2 tKL2 tKH2
SCK
tSIK2
tKSI2
SB0, 1
tKSO2
65
PD753012, 753016, 753017
Serial transfer timing Bus release signal transfer
tKCY3, 4 tKL3, 4 tKH3, 4
SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4
SB0, 1 tKSO3, 4
Command signal transfer
tKCY3, 4 tKL3, 4 SCK tKSB tSBK tSIK3, 4 tKSI3, 4 tKH3, 4
SB0, 1 tKSO3, 4
Interrupt input timing
tINTL tINTH
INT0, 1, 2, 4 KR0-7
RESET input timing
tRSL
RESET
66
PD753012, 753016, 753017
Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = -40 to +85 C)
Parameter Release signal setup time Oscillation stabilization wait time Note 1 Symbol tSREL tWAIT Released by RESET Released by interrupt request Conditions MIN. 0 Note 2 Note 3 TYP. MAX. Unit
s
ms ms
Notes 1. 2. 3.
The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. Either 217/fX or 2 15/fX can be selected by mask option. Set by the basic interval timer mode register (BTM). (Refer to the table below.)
BTM3 - - - -
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 fx = 4.19 MHz 0 1 1 1 220/fx
Wait Time fx = 6.0 MHz 2 20/fx (approx. 175 ms) 2 17/fx (approx. 21.8 ms) 2 15/fx (approx. 5.46 ms) 2 13/fx (approx. 1.37 ms)
(approx. 250 ms)
217/fx (approx. 31.3 ms) 215/fx (approx. 7.82 ms) 213/fx (approx. 1.95 ms)
Data retention timing (when STOP mode released by RESET)
Internal reset operation Oscillation stabilization wait time STOP mode Data retention mode Operation mode
VDD STOP instruction execution
tSREL
RESET
tWAIT
Data retention timing (standby release signal: when STOP mode released by interrupt signal)
Oscillation stabilization wait time STOP mode Data retention mode Operation mode
VDD STOP instruction execution Standby release signal (interrupt request)
VDDDR
tSREL
tWAIT
67
PD753012, 753016, 753017
13 . PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end
CD
S Q R
80 1
21 20
F G H P I
M
J K M N L
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX.
INCHES 0.6770.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.0040.004 55 0.119 MAX. S80GC-65-3B9-5
68
PD753012, 753016, 753017
80 PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60 61
41 40
detail of lead end
C
D
S Q R
80 1 20
21
F G P H I
M
J K M
N
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.000.20 12.000.20 12.000.20 14.000.20 1.25 1.25 0.22 +0.05 -0.04 0.10 0.50 (T.P.) 1.000.20 0.500.20 0.145 +0.055 -0.045 0.10 1.05 0.100.05 55 1.27 MAX. INCHES 0.5510.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.5510.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.041 0.0040.002 55 0.050 MAX. P80GK-50-BE9-5
69
PD753012, 753016, 753017
14. RECOMMENDED SOLDERING CONDITIONS
Solder the PD753017 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 14-1. Soldering Conditions of Surface Mount Type (1) PD753012GC-XXX-3B9: 80-pin plastic QFP (14 x 14 mm)
PD753016GC-XXX-3B9: 80-pin plastic QFP (14 x 14 mm) PD753017GC-XXX-3B9: 80-pin plastic QFP (14 x 14 mm)
Symbol of Recommended Condition IR35-00-3 VP15-00-3 WS60-00-1
Soldering Method Infrared reflow VPS Wave soldering
Soldering Conditions Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), Number of times: 3 max. Package peak temperature: 215 C, Time: 40 seconds max. (200 C min.), Number of times: 3 max. Solder bath temperature: 260 C max., Time: 10 seconds max., Number of times: 1 Preheating temperature: 120 C max. (package surface temperature) Pin temperature: 300 C max., Time: 3 seconds max. (per side of device)
Partial heating
-
Caution Do not use two or more soldering methods in combination (except partial heating).
70
PD753012, 753016, 753017
(2) PD753012GK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
PD753016GK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm) PD753017GK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
Symbol of Recommended Condition IR35-107-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), Number of times: 2 max., Number of days: 7Note (After that, prebaking is necessary at 125 C for 10 hours.) Products other than those packed in heat-resistant trays (such as those packed in a magazine, taping, or non-heat-resistant tray) cannot be baked while they are in their packaging.
VPS
Package peak temperature: 215 C, Time: 40 seconds max. (200 C min.), Number of times: 2 max., Number of days: 7Note (After that, prebaking is necessary at 125 C for 10 hours.) Products other than those packed in heat-resistant trays (such as those packed in a magazine, taping, or non-heat-resistant tray) cannot be baked while they are in their packaging.
VP15-107-2
Pin partial heating
Pin temperature: 300 C max., Time: 3 seconds max. (per side of device)
-
Note
The number of days for storage after the dry pack has been opened. 25 C, 65% RH max.
The storing conditions are
Caution Do not use two or more soldering methods in combination (except partial heating).
71
PD753012, 753016, 753017
APPENDIX A PD75316B, 753017 AND 75P3018 FUNCTION LIST
Parameter Program memory
PD75316B
Mask ROM 0000H-3F7FH (16256 x 8 bits)
PD753017
Mask ROM 0000H-5FFFH (24576 x 8 bits) 000H-3FFH (1024 x 4 bits)
PD75P3018
One-time PROM 0000H-7FFFH (32768 x 8 bits)
Data memory
CPU Instruction execution time When main system clock is selected When subsystem clock is selected Pin connection 44 47 48 50-53 57 Stack SBS register
Standard CPU 0.95, 1.91, 15.3 s (at 4.19 MHz operation) 122 s (32.768 kHz operation)
75XL CPU * 0.95, 1.91, 3.81, 15.3 s (at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (at 6.0 MHz operation)
P12/INT2 P21 P22/PCL P30-P33 IC None
P12/INT2/TI1/TI2 P21/PTO1 P22/PCL/PTO2 P30/MD0-P33/MD3 VPP SBS.3 = 1: Mk I mode selection SBS.3 = 0: Mk II mode selection n00H-nFFH (n = 0-3) Mk I mode: 2-byte stack Mk II mode: 3-byte stack
Stack area Subroutine call instruction stack operation Instruction BRA !addr1 CALLA !addr1 MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr CALLF !faddr Timer
000H-0FFH 2-byte stack
Unavailable
Mk I mode: unavailable Mk II mode: available Available
3 machine cycles 2 machine cycles 3 channels * Basic interval timer: 1 channel * 8-bit timer/event counter: 1 channel * Watch timer: 1 channel
Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles 5 channels * Basic interval timer/watchdog timer: 1 channel * 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter, carrier generator, or timer with gate) * Watch timer: 1 channel
72
PD753012, 753016, 753017
Parameter Clock output (PCL)
PD75316B
, 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation)
PD753017
PD75P3018
* , 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (Main system clock: at 6.0 MHz operation) * 2, 4, 32 kHz (Main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (Main system clock: at 6.0 MHz operation)
BUZ output
2 kHz (Main system clock: at 4.19 MHz operation)
Serial interface
3 modes are available * 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit * 2-wire serial I/O mode * SBI mode None Provided
SOS register
Feedback resistor cut flag (SOS.0) Sub-oscillator current cut flag (SOS.1)
None
Provided
Register bank selection register (RBS) Standby release by INT0 Vectored interrupt Supply voltage Operation ambient temperature Package
None No External: 3, internal: 3 VDD = 2.0 to 6.0 V TA = -40 to +85C
Yes Yes External: 3, internal: 5 VDD = 2.2 to 5.5 V
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm) * 80-pin plastic QFP (14 x 14 mm)
73
PD753012, 753016, 753017
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for system development using the PD753017. The 75XL series uses a common relocatable assembler, in combination with a device file matching each machine. Language processor
RA75X relocatable assembler Part Number (product name)
Host Machine OS PC-9800 series MS-DOSTM Ver. 3.30 to Ver. 6.2 IBM PC/ATTM and compatible machines Refer to OS for IBM PC
Note
Distribution media 3.5-inch 2HD 5-inch 2HD
S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X
3.5-inch 2HC 5-inch 2HC
Device file
Host Machine OS PC-9800 series MS-DOSTM Ver. 3.30 to Ver. 6.2 IBM PC/AT and compatible machines Refer to OS for IBM PC
Note
Distribution media 3.5-inch 2HD 5-inch 2HD
Part Number (product name)
S5A13DF753017 S5A10DF753017 S7B13DF753017 S7B10DF753017
3.5-inch 2HC 5-inch 2HC
Note
Ver. 5.00 and later have the task swap function, but cannot be used for this software. The operation of the assembler and device file is guaranteed only on the above host machines and OSs.
Remark
74
PD753012, 753016, 753017
PROM write tools
Hardware PG-1500 PG-1500 is a PROM programmer which enables you to program single chip microcomputers containing PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256K bits to 4M bits. PROM programmer adapter for PD75P3018GC. Connect the programmer adapter to PG1500 for use. PA-75P316BGK PROM programmer adapter for PD75P3018GK. Connect the programmer adapter to PG1500 for use. PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2Note IBM PC/AT and compatible machines Refer to OS for IBM PC 3.5-inch 2HC 5-inch 2HC Distribution media 3.5-inch 2HD 5-inch 2HD Part number (product name)
PA-75P316BGC
Software
PG-1500 controller
S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500
Note
Ver.5.00 and later have the task swap function, but it cannot be used for this software.
Remark The operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.
75
PD753012, 753016, 753017
Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the
PD753017.
The system configurations are described as follows.
Hardware IE-75000-RNote1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a PD753017 subseries, the emulation board IE-75300-R-EM and emulation probe that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a
IE-75001-R
PD753017 sub-series, the emulation board IE-75300-R-EM and emulation probe which are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer.
IE-75300-R-EM Emulation board for evaluating the application systems that use the PD753017 subseries. It must be used with the IE-75000-R or IE-75001-R. Emulation probe for the PD753017GC. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 80-pin conversion socket EV-9200GC-80 which facilitates connection to a target system. Emulation probe for the PD753017GK. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 80-pin conversion adapter TGK-080SDW which facilitates connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the above hardware on a host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2Note 3 IBM PC/AT and its compatible machines Refer to OS for IBM PC 3.5-inch 2HC 5-inch 2HC Distribution media 3.5-inch 2HD 5-inch 2HD Part number (product name)
EP-753017GC-R
EV-9200GC-80 EP-753017GK-R
TGK-080SDWNote 2 Software IE control program
S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X
Notes 1. 2. 3.
Maintenance parts This is a product of Tokyo Eletech Corp. (Tokyo 03-5295-1661) When purchasing this product, consult your NEC distributor. Ver.5.00 and later have the task swap function, but it cannot be used for this software.
Remark The operation of the IE control program is guaranteed only on the above host machines and OSs.
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OS for IBM PC The following IBM PC OS's are supported.
OS PC DOS TM Version Ver. 3.1 to Ver. 6.3 J6.1/V Note to J6.3/V Note Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/V Note J5.02/V Note
MS-DOS
IBM DOS TM
Note
Only English version is supported.
Caution Ver. 5.0 and later have the task swap function, but it cannot be used for this software.
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APPENDIX C RELATED DOCUMENTS
Some of the following related documents are preliminary. Device Related Documents
Document No. Japanese English U10140E (This manual) U10956E U11282E - U10453E
Document Name
PD753012, 753016, 753017 Data Sheet PD75P3018 Data Sheet PD753017 User's Manual PD753017 Instruction
75XL Series Selection Guide
U10140J U10956J U11282J IEM-5598 U10453J
Development Tool Related Documents
Document No. Japanese IE-75000 R/IE-75001-R User's Manual Hardware IE-75300-R-EM User's Manual EP-753017GC/GK-R User's Manual PG-1500 User's Manual RA75X Assembler Package User's Manual Software PG-1500 Controller User's Manual Operation Language PC-9800 Series (MS-DOS) Base IBM PC Series (PC DOS) Base EEU-846 U11354J EEU-967 U11940J U12622J U12385J EEU-704 EEU-5008 English EEU-1416 U11354E EEU-1494 U11940E EEU-1346 EEU-1363 EEU-1291 U10540E
Document Name
Other Documents
Document No. Japanese IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Devices Quality Guarantee Guide Guide for Products Related to Microcomputer : Other Companies C10535J C11531J C10983J C11892J C11893J U11416J C10943X C10535E C11531E C10983E C11892E MEI-1202 - English
Document Name
Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents.
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PD753012, 753016, 753017
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
2

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